Many computer-based products aim to save power while providing performance that is acceptable to users. Power-saving is especially critical in handheld, portable, possibly wireless, products where battery life is a primary and essential operational issue. Achieving power savings for a given electronic product (or circuit) requires consideration of its power-using features and associated functions. Typical considerations include: the modes in which the product operates, when a function/feature is doing useful work, whether a function is required to operate continuously, whether a function can be interrupted and then resumed as needed, alternative power saving methods and inconvenience to the user of the power-controlled product.
Typical computer systems include many different functional blocks. Blocks can operate synchronously or asynchronously and can be executed periodically or on demand. Also, each functional block performs a specific task. Given these variables, different power saving techniques may be required for each individual function or operation. The effectiveness of a power saving technique depends on how well the different operating conditions are handled for the majority of the system's power-critical functions.
A common target for power savings in computers, especially portable computers, is the display subsystem, which typically is one of the most power-consuming elements of a computer. For example, in some portable systems the power consumed by the display subsystem can be as high as 80-90% of total system power. Why this is so is described below in reference to FIG. 1, which shows a block diagram of a typical display subsystem 110 for an integrated device (i.e., a computer in which memory, display and CPU functions are integrated into a single chip). Display sub-systems for other computers, where a subset of these functions are implemented on individual chips, operate in a similar manner.
As shown in FIG. 1, the display sub-system of an integrated device 110 comprises a single-chip computer 112, a memory bank 120 and a display panel 130. The single-chip computer 112 includes a CPU 114, a memory controller 118 and a display processor 116. Data (including addresses and display data 122) and memory control commands are transferred between the memory controller 118 and the memory bank 120 via a memory bus 140. Display data from the memory 120 are transferred between the memory controller 118 and the integrated display processor 116 via an internal display channel 142. Pixel data 152 (i.e., graphics signals) and display panel control signals are transferred via a display connector 150 from the display processor 116 to the display panel 130, which generates a corresponding image.
The memory 120, which could be dedicated text, graphics, or video memory or unified memory implemented in accordance with a unified memory architecture (UMA), stores the display data 124, which is used by the display processor 116 to generate the pixel data 152. Each time the display processor 116 needs to generate a new frame of pixel data 152, the memory controller 118 must retrieve the appropriate graphics data 122 from the memory 120 over the display bus 140. The display processor 116 performs a number of operations on the display data 122 to generate the pixel data 152, including: synchronizing the pixel rate of the pixel data 152 to match the display panel's horizontal and vertical scan rate, performing gray-scale or color conversion and mapping (i.e., adjusting the number of colors represented by each pixel) and modifying the data formatting (e.g., pixel resolution). The display processor 116 can also control the display panel's mode of operation by adjusting display power and backlighting to save power as necessary.
Display operations are constant and continuous once enabled. Due to the inherent nature of display media, display images are constantly updated to maintain flicker-free images at all times. To eliminate flickering effects completely, the entire image is refreshed by the display processor 116 at a rate equal to or faster than 1/60th of a second (i.e., at a rate of greater than 60 frames/second). Power consumption by display sub-systems is high due to these continuous, high-frequency and memory-intensive operations. As a result, it is common for portable computers to provide a power saving option that completely disables the display when it is not in use. This option is not satisfactory when the computer is still in operation (albeit, not active use) as it prevents a user from viewing the display.
The power consumed by the display subsystem 110 for a given frame update depends on the resolution at which the update is to be performed and the number of colors in the image. This is because these factors determine the number of bits of display data 122 that must be transferred between the memory 120 and the memory controller 118 for each frame update and the number of display processor 116 cycles needed to compute the corresponding pixel data 152. For example, for a screen-resolution of 640.times.480 pixels displayable in 16 colors (or 4 bits per pixel), 9.216 MB of data transfer/processing is required to display an image (at 60 frames/second) for one second. Considerably more data transfer/processing (62.915 MB) is required to display an image (at 60 frames/second) for one second at a screen-resolution of 1024.times.1024 pixels displayable in 256 colors (or 8 bits per pixel).
These operations, especially the transfer of data over the memory bus 140 are power-intensive. Therefore, to achieve substantial power savings without turning off the display sub-system it is necessary to reduce significantly the memory cycles required to generate a display frame. Moreover, because these memory cycles consume a large percentage of the total available system bus bandwidth, reducing memory cycles also improves system performance by increasing the available system bus bandwidth for other system activities. The exact bandwidth improvement due to reducing memory cycles depends on the display resolution and the number of displayable colors.
Many prior art display processors have adopted a solution to reduce these memory cycles wherein the display data 122 stored in the memory 120 is compressed. In these systems the compressed data is used to generate a corresponding frame of graphics data. This eliminates the need to transfer repeatedly over the memory bus 140 the uncompressed data from which the compressed data 122 was generated. Depending on the compression rate (i.e., the ratio by which the compressed data 122 is smaller than the corresponding uncompressed data), large amounts of power can be saved by this technique. Problems with this technique include: (1) the need to rapidly compress the data so that it is available for immediate use and (2) the fact that the compression must be lossless or near-lossless so that a user viewing the display is not unduly inconvenienced. Moreover, these techniques are not sensitive to the manner in which the computer associated with the display is being used. For example, they do distinguish between when the system is in active use or when it is standing-by for user input, which is a state in which computers spend much of their time.